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High-Performance Damascene-Gate Thin Film Transistors

Published online by Cambridge University Press:  15 February 2011

Eugene Ma  and
Sigurd Wagner
Eugene Ma
Affiliation:
Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
Sigurd Wagner
Affiliation:
Department of Electrical Engineering, Princeton University, Princeton, NJ 08544
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Abstract

We report a novel TFT structure where the gate metal is embedded into a SiNx passivation layer. This allows the subsequent gate dielectric layer to be much thinner than in conventional bottom-gate structures. thereby reducing the threshold voltage and the sub-threshold slope. TFTs employing these damascene-gate structures were fabricated with SiNX gate dielectrics as thin as 50 nm. Such devices exhibit threshold voltages of 0.9 V, sub-threshold slopes of 0.1 V/dec, ION/IOFF current ratios of 106 and linear region field-effect mobilities of 0.6 cm2/Vs.

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