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Hall Mobility in Strained SiGe p-Mosfets

Published online by Cambridge University Press:  15 February 2011

L. Garchery ,
I. Sagnes ,
Y. Campidelli ,
M. Berenguer ,
P.A. Badoz ,
Y. Guldner  and
S. Zanier
L. Garchery
Affiliation:
FRANCE TELECOM-CNET, BP 98, 38243 MEYLAN Cedex, FRANCE
I. Sagnes
Affiliation:
FRANCE TELECOM-CNET, BP 98, 38243 MEYLAN Cedex, FRANCE
Y. Campidelli
Affiliation:
FRANCE TELECOM-CNET, BP 98, 38243 MEYLAN Cedex, FRANCE
M. Berenguer
Affiliation:
FRANCE TELECOM-CNET, BP 98, 38243 MEYLAN Cedex, FRANCE
P.A. Badoz
Affiliation:
FRANCE TELECOM-CNET, BP 98, 38243 MEYLAN Cedex, FRANCE
Y. Guldner
Affiliation:
LPMC, ENS, 24 rue Lhomond, 75005 PARIS, FRANCE
S. Zanier
Affiliation:
LPMC, ENS, 24 rue Lhomond, 75005 PARIS, FRANCE
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Extract

One of the limiting factors in the performance of future CMOS integrated circuits is the low hole mobility which causes the transconductance of p-channel transistors to be inferior to those of n-channel devices. One promising way of enhancing hole mobility is to introduce a buried SiGe layer under the gate of p-MOS transistors. The mobility improvement thus results from, i) reduction in surface scattering (by moving carriers away from scattering sites at the Si/SiO2 interface), and ii) higher in-plane hole mobility in biaxally strained SiGe layers.

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References

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