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Characterization of Metal-Ferroelectric-Metal-Insulator-Semiconductor (MFMIS) FETs Using (Sr,Sm)0.8Bi2.2Ta2O9 (SSBT) Thin Films

Published online by Cambridge University Press:  01 February 2011

Hirokazu Saiki  and
Eisuke Tokumitsu
Hirokazu Saiki
Affiliation:
Precision and Intelligence Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama, 226–8503, Japan
Eisuke Tokumitsu
Affiliation:
Precision and Intelligence Laboratory, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama, 226–8503, Japan IT-21 Center, Research Institute of Electrical Communication, Tohoku University, 2–1–1 Katahira, Aoba-ku, Sendai, 980–8577, Japan
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Abstract

We have fabricated and characterized Pt (60nm) / (Sr,Sm)0.8Bi2.2Ta2O9 (SSBT, 130nm) / Pt (60nm) / Ti (10nm) / SiO2 (10nm) / p-Si (MFMIS:metal-ferroelectric-metal-insulator-semiconductor) structure FETs. The area ratio, the ratio of SSBT capacitor area to SiO2 capacitor, is varied from 1 to 15 in the MFMIS-FETs. It is demonstrated that MFMIS-FETs with area ratio of 6 have memory window of 0.5V with supply voltage of 5 V. Dependence of memory window on the area ratio is discussed.

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Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 784: Symposium C – Ferroelectric Thin Films XII , 2003 , C9.8/E9.8
Copyright
Copyright © Materials Research Society 2004

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References

REFERENCES

1. Ross, I. M., US Patent 2791760 (1957).Google Scholar
2. Moll, J. L. and Tarui, Y., IEEE Trans. Electron Devices ED-10, 333 (1963).Google Scholar
3. Sugibuchi, K., Kurogi, Y. and Endo, N., J. Appl. Phys. 46, 2877 (1975).Google Scholar
4. Higuma, Y., Matsui, Y., Okuyama, M., Nakagawa, T. and Hamakawa, Y., Proc, 9th Conf. Solid State Devices, Tokyo 1977, Jpn, J. Appl. Phys. Suppl. 17–1, 209 (1978).Google Scholar
5. Nakao, Y., Nakamura, T., Kamisawa, A. and Takasu, H., Integr. Ferroelectr. 6, 23 (1995).Google Scholar
6. Nakamura, T., Nakao, Y., Kamisawa, A. and Takasu, H., Integr. Ferroelectr. 9, 179 (1995).Google Scholar
7. Hirai, T., Fujisaki, Y., Nagashima, K., Koike, H. and Tarui, Y., Jpn. J. Appl. Phys. 36, 5908 (1997).Google Scholar
8. Tokumitsu, E., Fujii, G. and Ishiwara, H., Appl. Phys. Lett. 75, 575 (1999).Google Scholar
9. Tokumitsu, E., Fujii, G. and Ishiwara, H., Jpn. J. Appl. Phys. 39, 2125 (2000).Google Scholar
10. Tokumitsu, E. and Kishi, M., Mat. Res. Soc. Pymp. Proc. 748, 275 (2002).Google Scholar
11. Tokumtisu, E., Kishi, M., Iseki, K., Fujisaki, Y. and Ishiwara, H., 2003 Asia-Pacific Workshop on Fundamental and Application of Advanced Semiconductor Devices, June 30-July 2, 2003, Busan, Korea.Google Scholar