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Rapid Thermal Processes for Future Nanometer MOS Devices

Published online by Cambridge University Press:  10 February 2011

John R. Hauser
John R. Hauser*
Affiliation:
ECE Department, North Carolina State University, Raleigh, NC 27695, hauser@eos.ncsu.edu
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Abstract

Scaling of MOS devices is projected to continue down to device dimensions of at least 50 nm. However, there are many potential roadblocks to achieving such dimensions and many standard materials and front-end processes which must be significantly changed to achieve these goals. The most important areas for change include (a) gate dielectric materials, (b) gate contact material, (c) source/drain contacting structure and (d) fundamental bulk CMOS structure. These projected changes are reviewed along with possible applications of rapid thermal processing to achieving future nanometer scale MOS devices.

Information

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 525: Symposium W – Rapid Thermal & Integrated Processing VII , 1998 , 171
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

1. SIA, “National Technology Roadmap for Semiconductors”, 1997 EditionGoogle Scholar
2. Taner, Y., Buchanan, D.A., Chen, W., Frank, D.J., Ismail, K.E., Lo, S.-H., Sai-Habasa, G.A., Visivanatham, R.C., Wann, H.-J.C., Wind, S.J. and Wong, H.-S., “CMOS Scaling into the Nanometer Regime”, Proc. of the IEEE 85, 486 (19).Google Scholar
3. Momose, H.S., Ono, M., Yoshitomi, T., Ohgmo, T., Nakamma, S., Saito, M. and Iwai, H., “Tunneling Gate Oxide Approach to Ultra-High Current Device in Small Geometry MOSFETs”, IEDM Tech. Dig. 593 (1994).Google Scholar
4. Vogel, E.M., Ahmed, K.Z., Hornung, B., Henson, W.K., McLarty, P.K., Lucovsky, G., Hauser, J.R., and Wortman, J.J., “Modeled Tunnel Currents for High Dielectric Constant Dielectrics”, accepted for pub, IEEE Trans. on Elec. Dev.Google Scholar
5. Yang, H.Y., Niimi, H., and Lucovsky, G., “Tunneling Currents Through Ultrathin Oxide/Nitride Dual Layer Dielectrics for Advanced Microelectronic Devices”, JAP 83, 2327 (1998)Google Scholar
6. Sanganeria, M.K., Violett, K.E. and Öztürk, M.C., “Boron Incorporation in Epitaxial Silicon Using Si2H6 and B2H6 in an Ultrahigh Vacuum Rapid Thermal Chemical Vapor Deposition Reactor”, J. of Electrochem. Soc. 142, 285 (1995).Google Scholar
7. Ng, K.K. and Lynch, W.T., “Analysis of the Gate-Voltage-Dependent Series Resistance of MOSFETs”, IEEE Trans. on Ed. ED–33, 965 (1986).Google Scholar
8. Ng, K.K. and Lynch, W.T., “The Impact of Intrinsic Series Resistance on MOSFET Scaling”, IEEE Trans. on ED ED–34, 503 (1987).Google Scholar
9. Chang, C.Y., Fang, Y.K. and Sze, S.M., “Specific Contact Resistance of Metal-Semiconductor Barriers”, Solid-State Elec. 14, 54 (1971).Google Scholar
10. Grider, D.T., Öztürk, M.C., Ashburn, S.P. and Wortman, J.J., “Ultra-Shallow Raised p+-n Junctions Formed by Diffusion from Selectively Deposited In Situ Doped Si0.Ge 0.3”, J. Of Elec. Mat. 24, 1369 (1995).Google Scholar
11. Violette, K.E., O'Neil, P.A. and Öztürk, M.C., “Low Temperature Selective Silicon Epitaxy by Ultra High Vacuum Rapid Thermal Chemical Vapor Deposition Using Si2H6, H2 and C12”, Appl. Phys. Lett. 68, 66 (1996).Google Scholar
12. Öztürk, M.C., Weintraub, C.E. and Batchelor, D.E., “Chemical Vapor Deposition of Titanium Silicide on Boron and Arsenic Implanted Silicon”, Submitted to IEEE Trans. on ED.Google Scholar