The explosive growth under way in the performance of digital electronicsystems is directly traceable to the impact of Si MOS device scaling and itsaccompanying increase in functionality at the chip level. The increasingdata rates and chip I/O that have accompanied this scaling have driven theevolution of both system architectures and the interconnection and packagingtechnologies (i.e. chip carriers, printed circuit boards, bus structures)that support this CMOS functionality and dominate overall system volume. Thefurther scaling of CMOS technology towards 0.1 – 2.5μmminimum gate lengths coupled with modest increases in chip size (i.e. 2–4cm), promise upwards of a 100 fold increase in chip-level complexity. Theresulting emergence of Ultra Large Scale Integrated (ULSI) processor arraychips and wafer-scale memory (solid state disks) hold the potential forextremely compact distributed computing systems. Through a continuation ofthe evolutionary trends of system scaling, application of chip level processtechnology to higher system levels, and mixed technology integration (e.g.BiCMOS); present advanced packaging technologies based upon Multi-ChipModules (MCM) will mature into hybrid wafer-level three-dimensional siliconsystems allowing burdensome driver and communication control functions nowdesigned at the chip level to move off chip into the active siliconinterconnection substrate where network transmission and control can both beimplemented. Realization of the performance potential of these silicon ULSIsystems will largely depend on the successful implementation of thiswafer-level communication network linking the high-density of processingnodes. The role that any advanced technology (i.e. high-speed normalelectronic, superconducting, optical) will serve within this network will bedetermined by the degree of connectivity it can achieve in this scaledenvironment and by its ability to benignly coexist with the dominant CMOStechnology, the network's physical and functional foundation[l].